Certification in ASIC Verification (Duration: 10 weeks)

• Motivation: With the complexity of today’s SOCs, there is a shortage of qualified engineering staff to perform quality verification of the design.
• Teachers: Experienced Engineers from industry teach the classes and guide on the lab work, and so prepare the students to enter the industry with full confidence, and be productive sooner than later.
• Eligibility: Competency in C/C++ programming with knowledge of logic design concepts.
• Placement: Assist the students in placement in technology start-ups and MNCs.
• Fee: Please contact and apply online to know the fee details. (Coming Soon!!)
• Students: Click Here to Apply Online
• Employers: Please email us at employer@krispan.com with your contact details and we will get back to you.

Structure
Total: 10 weeks

• 6 hours of lecture each week
• 8 hours of lab each week.

COURSE OUTLINE:
LECTURE

• Anatomy of System On Chip (SoC) Systems
• Basic Logic Gates
• Fundamentals of Logic Design
• Understanding State Machines
• Test-bench Concepts
• Verification Flows
• Types of Test Benches
• Architecture concepts of a testbench
• Verilog for Verification
• Verification Languages and Methodologies
• Constrained Random Verification
• Verification IP Integration

HVLS – HIGH LEVELVERIFICATION LANGUAGES AND METHODOLOGIES

1. SystemVerilog
2. System C

1. Unified Verification Methodology (UVM)

COURSE PROJECT

Project involves architecting and building up a complete Testbench using SystemVerilog and UVM.

For more information on this training module please click on button below;

Current class registration is closed right now. We will be offering this class again, send request if you are interested in this training. Also, see our other Krispan Technical Training Classes Offered.

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