Sr. Verification Engineer

Seven or more years of experience with various verification flows, with a proven track record of delivering successful ASICs in production.

• Should be experienced in Architecting a verification environment for multi million gate ASICs.
• Candidate should have worked on at least two full chip Verifications involving Test Plan, Development and Execution.
• Experience with object oriented verification languages SystemVerilog and C++ is a must.
• Experience with Verilog is a must.
• Expertise in one or more Verification Methodologies like OVM/VMM/UVM is preferred.
• Experience with Assertions and Coverage
• Having a Design Engineering background is a plus.
• Should have knowledge of Networking or SoC Protocols like 802.3, 802.11, PCIe, DDR2/3, AMBA AHB/AXI
• Should be a power user of scripting languages like Perl/Tcl.

Qualifications:
BSEE Must
MSEE Preferred

Senior Consulting Hardware Design (FPGA) Engineer

Five to Seven years of experience in hardware design, lab debug, scripting , FPGA design, and Embedded systems design.

• Experience with Verilog, C, C++ coding.
• FPGA Design, Debug, Verification, and Synthesis.
• FPGA timing closure.
• FPGA bring up.
• FPGA System Integration.
• Good understanding of Microprocessor Architecture.
• Good knowledge of interrupts and managing interrupt threads.
• Good knowledge of perl and python scripting.
• Some embedded systems Firmware experience.
• DSP implementation a plus.
• Mixed signal knowledge a plus.

Qualifications:
BSEE minimum
MSEE preferred
Must have good communication Skills

If Interested, please send your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it

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Senior Consulting Verification Engineer

Seven or more years of experience with various verification flows, with a proven track record of delivering successful ASICs in production.

• Should be experienced in Architecting a verification environment for multi million gate ASICs.
• Candidate should have worked on at least two SOC Verifications involving Test Plan, Development and Execution.
• Experience with object oriented verification languages SystemVerilog and SystemC is a must.
• Expertise in one or more Verification Methodologies like OVM/VMM/UVM is required.
• Experience with Assertions and Coverage
• Experience with Specman is a PLUS
• Having a Design Engineering background is a plus.
• Should have knowledge of SoC Protocols like PCIe, DDR2/3, AMBA AHB/AXI
• Should be a power user of scripting languages like Perl/Tcl.

Qualifications:
BSEE minimum
MSEE preferred

If Interested, please send your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it

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Senior Consulting Physical Design (Backend) Engineer

Seven or more years of experience in running STA analysis and providing timing closure on multiple high performance low power chips.

• Develop, own, and maintain Place and Route methodologies and scripts for full RTL2GDS.
• Responsible for Placement, Routing, Extraction, Power IR and EM of block level and full chip.
• Work closely with frontend engineers for timing closure activities.
• Experienced in back-end design flows.
• Experiences with back-end place-and-route tool(IC Compiler prefered),
• Familiarity with RC extraction
• Experience with Layout verification tools (Calibre) and Layout editors.
• Expertise with physical design flow and methodology for deep sub-micron processes.
• Candidate should have developed full chip timing constraints for complex, multi-voltage, multi-clock SOC.
• Good perl and TCL scripting skills
• Experience with ECO generation scripts for quick turn around.
• Experience on clock path simulation with SPICE is a plus.
• Enhance entire timing flow from frontend to backend at both chip and block level.
• Experience with Synopsys' ICC Compiler is a BIG plus.

Qualifications:
BSEE minimum
MSEE preferred
Must have good communication Skills

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Sr. Consulting Timing Engineer

Senior Consulting STA(Timing) Engineer

Seven or more years of experience in running STA analysis and providing timing closure on multiple high performance low power chips.

• Proficient in developing and supporting full automated STA scripts/flows using Synopsys Prime Time.
• Candidate should have developed full chip timing constraints for complex, multi-voltage, multi-clock SOC.
• Good perl and TCL scripting skills (especially in prime time).
• Develop or enhance timing related scripts for critical path analysis, clock skew analysis, various macro interfaces.
• Experience with constraint partitioning, IO timing budgeting, and SDC cleanup.
• Experience with ECO generation scripts for quick timing closure.
• Experience on clock path simulation with SPICE is a plus.
• Enhance entire timing flow from frontend to backend at both chip and block level.
• Experience with backend tools is a plus.

Qualifications:
BSEE minimum
MSEE preferred

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Junior Firmware QA Engineer

Job Description

• QA testing of FW
• QA platform development in Python scripting environment
• Generates test flow data for post analysis tools
• QA test platform design, development in Python scripting environment
• Will be involved in FW tasks

Required Skills and experience

• Must have in depth knowledge of scripting with Python
• Must have experience in QA test platforms and automation
• Experience of 1-3 years as Firmware/QA Engineer.
• BS in EE/CS, MS Preferred

Nice to have skills

• Some Experience with Tensilica Firmware
• Scripting in Shell and Perl
• Expertise with C/C++ for embedded software

If Interested, please send your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it

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Principal Verification Engineer

Should be an expert in Architecting a verification environment for multi million gate ASICs. Expertise with object oriented verification languages like Vera/SystemVerilog is a must. Having a Design Engineering background is a plus. Should be a power user of scripting languages like Perl/Tcl.

Experience with tools like VCS, Debussy is a must.

Knowledge of wireless and wired networking protocols is a big plus.

Qualifications:
BSEE minimum
MSEE preferred

Ten or more years of experience with various verification flows, with a proven track record of delivering successful ASICs in production.

If Interested, please send your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it

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Senior Verification Engineer

Should be experienced in Architecting a verification environment for multi million gate ASICs. Expertise with object oriented verification languages like Vera/SystemVerilog is a must. Having a Design Engineering background is a plus. Should be a power user of scripting languages like Perl/Tcl.

Experience with tools like VCS, Debussy is a must.

Knowledge of wireless and wired networking protocols is a big plus.

Qualifications:
BSEE minimum
MSEE preferred

Seven or more years of experience with various verification flows, with a proven track record of delivering successful ASICs in production.

If Interested, please send your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it

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Senior Design Engineer (two openings).

Should be experienced in Architecture/Design of multi million gate ASICs. Expertise with Verilog is a must. Should have worked on Design and verification of individual blocks as well as top level blocks.

Should be very comfortable with Synthesis and timing with tools like SYNOPSYS DC/PT.

Knowledge of wireless and wired networking protocols is a big plus.

Expertise with

Qualifications:
BSEE minimum
MSEE preferred

Seven or more years of experience of working on various designs, with a proven track record of delivering successful ASICs in production.

If Interested, please send your resume to This e-mail address is being protected from spambots. You need JavaScript enabled to view it